MIPS R2000
Realizes: Early SGI and DECstation workstations
Introduced in 1985 with a five-stage RISC pipeline, the MIPS R2000 leaned on single-cycle integer basics, a concise load/store ISA, and predictable control flow to keep each stage decoding, executing, and retiring in lockstep, which made it attractive to early SGI and DEC workstation vendors.
Examples
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SGI Indigo workstation
The SGI Indigo workstation used the R2000 (and R3000) to deliver graphics and engineering performance in the early 1990s, showcasing its pipeline-driven throughput.
[INTEGER-ALU,LOAD-STORE,PIPELINED]
microseconds
large
mJ